1. Field of the Invention
The present invention relates to an integrated circuit that includes an array of memory cells.
2. Description of the Prior Art
Integrated circuits that include memories typically comprise an array of memory cells arranged in rows and columns. For example, an illustrative memory design 100 is shown in FIG. 1. The memory cells 107-109 may be of the static type, for example, in which case each cell typically comprises four cross-coupled transistors, or alternatively two cross-couple transistors each having load resistors. The access transistors 110-115 conduct, thereby provide access to the memory cells in the illustrated row, when the row conductor 117 is activated. That is, when the access transistors are n-channel devices, a high row conductor voltage allows access to the memory cells from the corresponding column conductors 118-123. The column conductors are alternatively referred to as "bit lines" in the art, since a single bit of information is read from a given memory cell, or written into a given memory cell, in a given selected column. The row selection circuitry, column selection circuit, and sense amplifiers that increase the signal level from the memory cells are well known in the art, and not shown in FIG. 1. It will also be understood by persons of skill in the art that static memories are bistable devices having two nodes that are stable in opposite voltage levels, and access to both nodes is typically desired. However, dynamic memory cells used in dynamic random access memory (DRAM), and read only memory (ROM) cells are usually of a single-ended design, requiring only a single access transistor and a single column conductor per column of memory cells.
During each memory cycle, and prior to a given access operation, the column conductors are precharged to a high voltage level. That is, when the voltage on the precharge line 116 goes high, the precharge transistors 101-106 momentarily conduct, thereby pulling the voltage on the column conductors toward the positive power supply voltage V.sub.DD. However, in the illustrated case, the threshold voltage drop across the n-channel precharge transistors (V.sub.tn) causes the column conductors to be precharged to only a threshold voltage below the power supply voltage (i.e., to V.sub.DD - V.sub.tn). This lowered precharge voltage is desirable in many cases, since it allows a faster read or write operation to the selected cells. For example, during a write operation, the lowered precharge voltage allows the write circuitry to drive the column conductors in the selected column toward opposite voltage levels (i.e., one toward V.sub.DD and the other toward V.sub.SS) at a faster rate than if they were precharged to the full V.sub.DD level. The lowered precharge voltage is especially significant during a read operation, when the relatively small current sinking capability of the selected memory cell must drive the zero-going column conductor rapidly toward V.sub.SS (zero volts). This is required so that the sense amplifier can detect the proper memory state (logic "1" or "0") stored in the selected cell within the prescribed access time, which is desirably as short as possible.
One condition that may occur during a precharge operation, and which is especially disruptive during a subsequent read operation, concerns noise on the positive power supply voltage V.sub.DD. That is, any positive noise voltages tend to increase the precharge voltage above the nominal design value. Such noise may be due to ground bounce on the negative power supply conductor, or changes in the power supply load due switching transients as output buffers switch, or various inductive and/or capacitive coupling effects, etc. However, whatever the cause, an increase in the precharge voltage is undesirable, since it increases the access time, especially during a read operation. This is because the memory cell must take a longer time to drive the zero-going column conductor sufficiently toward ground that the sense amplifier can detect the proper stored signal level. Therefore, the designer of the integrated circuit must allow sufficient time during a worst-case read operation to compensate for the longer access time in the case of maximum anticipated noise. A similar noise effect occurs during a write operation, but the larger current-drive capability of the write circuitry (not shown in FIG. 1) makes the penalty less severe.
Note that some prior-art designs provide for precharging the column conductors to the full V.sub.DD level. This is typically accomplished using p-channel precharge transistors activated by a low-going gate voltage, in lieu of the n-channel precharge transistors shown in FIG. 1. The above noise considerations still apply, except that the drain-to-substrate p-n junctions of the p-channel precharge transistors may limit the maximum noise voltage to one diode voltage drop (about 0.6 volts) above V.sub.DD.
In the prior art, one technique to alleviate the power supply noise problem is to add devices that provide a high-resistive leakage path to ground (V.sub.SS). For example, resistors 124-129 may be provided, which allow any noise-induced positive voltage spike to slowly decay. However, this technique dose not help for fast noise. This is because the resistors must be made sufficiently large, each having a value typically in the range of hundreds of megohms to several gigaohms, that the readout signal from the memory cells is not impaired due to excessive loading. Otherwise, the drive capability of the memory cells would have to be increased. This is undesirable, considering that the most power dissipation of typical memory devices is contributed by the memory array. Furthermore, the increase drive capability would undesirably add to the size of the transistors in the memory cells, and hence to the size of the array. Therefore, an improved technique that provides for increased power supply noise immunity, while avoiding excessive loading effects, is desirable.